Production IC test ops need a rescue!  Current methods can't maintain favorable costs for next-gen devices.  This has been discussed for ages.  But ever-increasing density and test complexity, while budgets are shrinking, stress more than just the test floor.  Here are five aspects of the semiconductor roadmap that continue to be important and that motivate my projects.

The first challenge is to reduce the price of the tester hardware and all its associated real estate.  Enormous bays of very expensive and large testers, robotics, cooling and power conditioning equipment must be precisely scheduled to pass as many batches as possible, leaving no machine idle.  A development plan must fill that space more efficiently and then promote production flow.  It must also slash both acquisition and operating costs.

More challenges are attached to the increased importance of wafer testing as newer stacked dies prevail.  Getting to both sides of thru-silicon vias will be very expensive without breakthrough probing.  Testing both before and after assembly will require separate test development and better access to functions.  Software creation will have to take advantage of new technology to keep costs down.

New requirements to coordinate aspects of test planning with early design analysis, and to simultaneously advance each during the entire development process, are also opportunities to streamline.  The V model encourages both top-down and bottom-up methods writing across phases that belong to different sides of the diagram, like windows into parallel universes that must merge in time.

Add savings from design reuse, not just between devices, but now also through creating production tests from the same testbench designs used for simulation and prototyping.  Functional coverage measures from statistical verification can result in shorter production test times.

The science of testing continues inventing new approaches that may prove most suitable for any particular chip.  The test floor must be flexible without being expensively generic.  It ought to provide hardware appropriate to each targeted cost of test, and plenty of it.

So imagine a smaller, denser floor, where neither machine subsystems nor devices are left idle.  Imagine the most protective wafer probing, and greatly multiplied throughput.  Imagine that design and planning effort leave room for profit.  Imagine cost of ownership scaling linearly for a change.

Of course, startups and stalwarts are all aiming to provide exciting advances in these aspects of lowering the cost of production testing.  I've been able to influence some of those visions, and look forward to getting my unique pieces of the puzzle added to their successes.

We should talk at 503-614-0159.  You can also contact scott.swenson@orsyn.com.

I started my company in 1977.  With employees and associates I have been providing mature engineering design service and products ever since.  My specialties are developing system software (more efficiently by knowing the hardware too), designing tester hardware, and prototyping large RTL subsystems in FPGAs.  I am located in Hillsboro, Oregon.

I seek contracts, and can lead, work alone, or join any team.  I have served in all roles from marketing product definition, hardware/software/QA, to short-run production, each under varied product introduction environments.